Thin Film Laboratories

University of Tehran

 

 

University of Tehran

 

   

 

 

Name :Jaber Derakhshandeh

Born: April 8, 1975, Tabriz, Iran

Address: Institute of Electrical Engineering, Campus No. 2, North Kargar Avenue, Tehran, Iran, P.O.Box 14395/515 Tehran.Tel : +98‑21-88512365 

E-mail: derakhshad@yahoo.com, j.derakhsh@ece.ut.ac.ir

 

ELECTRONIC DEVICES FABRICATION (PhD)

Research Interests:

Nanometer CMOS Transistors, (FDSOI, FinFET, High K Materials)

Thin Film Transistors,

Carbon Nano Tubes Growth,

Low Temperature Silicon Crystallization,

Semiconductor Sensors,

Photonic Crystals

 JOURNAL PUBLICATIONS

1) J. Derakhshandeh, N. Golshani, S. Mohajerzadeh, "Current Assisted Germanium Induced Crystallization of amorphous silicon on glass", Journal of Thin Solid Films, 2002.

2) P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, M. Robertson and A. Tonita, "Stress-assisted nickel-induced crystallization of silicon on glass," Journal of Vacuum Science and Technology A (JVSTA), Vol. 22, No. 3, p.p. 966-970 May/Jun 2004.

3) Y. Abdi, J. Derakhshandeh, S. Mohajerzadeh, F. Nayeri, E. Arzi and M.D. Robertson, " Light Emitting Nano-porous silicon structures fabricated using a plasma hydrogenation technique”, Journal of Materials and Science Engineering B 2005.

 4) Y. Abdi, J. Koohsorkhi, J. Derakhshandeh, S. Mohajerzadeh, H. Hoseinzadegan, M.D. Robertson and C. Benet,  “PECVD-grown Carbon-nano-tubes on Silicon Substrates with an anomalous Nickel-seeded Tip-growth structure”, Journal of Materials and Science Engineering C 2005.

5) J. Derakhshandeh, Y. Abdi, S. Mohajerzadeh, H. Hosseinzadegan, E. Asl. Soleimani and H. Radamson " Fabrication of 100nm Gate length MOSFET’s using a novel carbon-nanotube-based nano-lithography “,  Journal of Materials and Science Engineering B 2005.

 

INTERNATIONAL CONFERENCES

1) J. Derakhshandeh, N. Golshani, S. Mohajerzadeh, "Low temperature Germanium Induced Crystallization of silicon in the presence of electric current", EMRS, 2002.

2) A. Akhavan, L. Rezaee, S. Mohajerzadeh, J. Derakhshandeh," Metal free Germanium Induced Crystallization of a-Si on glass", MRS 2002.

3) P. Hashemi, A. Khajooeizadeh, S. Mohajerzadeh, J. Derakhshandeh, M. Robertson, J.C. Bennett, "Stress-assisted Nickel-Induced Crystallization of Silicon on Glass ," presented at 11th Canadian Semiconductor Technology Conference(CSTC), Ottawa, Canada, August 2003.

 

4) J. Derakhshandeh, S. Mohajerzadeh, N. Golshani, M.D.Robertson, "Field Aided Germanium Induced Crystallization of Silicon on glass", MRS, 2003.

5) A.Abbasian, S.H.Rasouli, J.Derakhshandeh, A.Afzali-Kusha, and M.Nourani " Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications”, in proceeding of the 2003 south west symposium on mixed signal design, Las Vegas, USA, 23-25 February, pp.87-89, 2003.

6) P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, M. Robertson and A. Tonita, “The Investigation of Stress-Assisted Nickel-Induced Crystallization of Silicon on Glass by TEM and SEM ", presented at the 31st Annual Meeting of the Microscopical Society of Canada, May 2004.

7) J. Derakhshandeh, P. Hashemi, S. Mohajerzadeh, and A. Khajooeizadeh, "Low-Temperature Stress-Assisted Nickel-Induced Crystallization of Silicon on Glass," presented at the Iran Physics Conference, Tehran, Iran, PP. 145, September 2004.

8) J. Koohsorkhi, Y. Adbi, S. Mohajerzadeh, J. Derakhshandeh, H. Hosseinzadegan and A. Khakifirooz, “Application of Encapsulated PECVED-grown Carbon Nano-Structure Field-Emission Devices in Nanolithography” Nanotech, (2005).

9) J. Derakhshandeh, Y. Abdi, S. Mohajerzadeh, H. Hosseinzadegan, E. Asl. Soleimani and H. RadamsonFabrication of 100nm Gate length MOSFET’s using a novel carbon-nanotube-based nano-lithography “,EMRS spring meeting 2005. (Candidate for EMRS 2005 conference award)

 

10) Y. Abdi, J. Koohsorkhi, J. Derakhshandeh, S. Mohajerzadeh, H. Hoseinzadegan, M.D. Robertson and C. Benet,  “PECVD-grown Carbon-nano-tubes on Silicon Substrates with an anomalous Nickel-seeded Tip-growth structure”, EMRS spring meeting 2005.

11) Y. Abdi, J. Derakhshandeh, S. Mohajerzadeh, F. Nayeri, E. Arzi and M.D. Robertson, Light Emitting Nano-porous silicon structures fabricated using a plasma hydrogenation technique”, EMRS spring meeting 2005.

12) P. Hashemi, J. Derakhshandeh, B. Hekmatshoar, S. Mohajerzadeh, Y. Abdi, and M.D. Robertson, “Low Temperature Metal-Free Fabrication of polycrystalline Si and Ge TFT’s by PECVD Hydrogenation” Material Research Society conference (MRS 2005), San Francisco CA, USA, spring 2005, vol. 862, pp.A22.2.1-A22.2.6.

 

13) J.Koohsorkhi, Y.Abdi, S.Mohajerzadeh, J.Derakhshandeh, L.Rezaee, M.D.       Robertson,   “Self-Defined PECVED-grown Carbon Field-Emission Transistors with Applications in Electron Diffraction” presented at Material Research Society (MRS) spring meeting, San Francisco, CA, March28-April1 (2005).

 

14) P. Hashemi, Y. Abdi, S. Mohajerzadeh, J. Derakhshandeh, B. Hekmatshoar, E. Arzi, M. D. Robertson, “Low temperature growth of nano-crystalline silicon and germanium using Rf hydrogen plasma with application in thin film transistors,” presented at the Iran Phys. Conf., Iran,  Aug. 2005.

 

15) J. Derakhshandeh, B. kasiri, Y. Farazmand, N. Masoumi, Akbarzadeh." A Precise Model for Leakage Power Estimation in VLSI Circuits ". Presented at the 2005 International Workshop on System on chip, July 20 - July 24, 2005, Banff, Alberta – Canada.

 

16) P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, M. D. Robertson, A. Shayan Arani, and A. Afzali Kusha, "Characterization of low temperature stress-induced crystallization of a-si on flexible glass substrate by raman and transmission electron microscopy," presented at the IEEE 17th Intl. Conf. on Microelectronics, Islamabad, Dec. 2005.

17)  H.Sedaghat-Pisheh, Y.Abdi, S.Mohajerzadeh, J.Derakhshandeh, and A. Khodadadi, "PECVD-grown Vertically aligned carbon nanotubes suitable for inter-digital structures on (100) Si-based membranes", accepted for The International Carbon 2006 Conference,16th-21st July, 2006, Aberdeen, Scotland

18) J. Derakhshandeh, Y. Abdi, S. Mohajerzadeh,  M. Beikahmadi, E.Arzi,  M.D. Robertson, J.C.Bennett “Nano-scale MOSFET Devices Fabricated Using a Novel Carbon-Nanotube-based Lithography.” presented at Material Research Society (MRS) spring meeting, San Francisco, CA, March19-April1 (2006).

 

19)  J. Derakhshandeh, M. Beikahmadi, K. Baghban, Y. Abdi, S. Mohajerzadeh, “Fabrication of 100nm Gate length MOSFET’s using a novel carbon-nanotube-based nano-lithography” presented at ICEE2006, Amirkabir University, Tehran

 

EDUCATION

 Ph.D. (Electrical Engineering - Electronics - Device fabrication) University of Tehran, Tehran, IRAN, fall 2000 to summer 2005.

Project: Fabrication of 100nm Gate length MOSFET’s using a novel carbon-nanotube-based nano-lithography and Fabrication of poly silicon Thin Film Transistors at low temperature on flexible substrate.

Total average : 18.5/20

Area of Research: Semiconductor Devices and materials Fabrication.

 

 M.Sc. (Electrical Engineering - Electronics - Analog design and device fabrication). Sharif University of Technology, Tehran, IRAN, 1998-2000.

Graduated with GPA 17/20.00.

Project: Design and Fabrication of  Electron Beam Gun for Evaporation Systems.

Area of Research: Semiconductor Devices and materials.

 

B.Sc. (Electrical Engineering - Electronics). University of Tabriz, Tabriz, IRAN, 1993-1997.

Graduated with GPA 15.5/20.00.

Project: Design and Fabrication of  1000 channels remote control system for industrial applications.

Area of Research: Electronics.

 

 REFERENCES

1) Dr. Shamsodin Mohajerzadeh: (University of Tehran) smohajer@vlsi.uwaterloo.ca

2) Dr. Bijan Rashidian: (Sharif University of Technology) rashidia@sina.sharif.edu

3) Associate Professor Henry Radamson: (KTH University, Sweden) rad@imit.kth.se  

 

WORK EXPERIENCE

1998 -to 2000            Research assistant, Micro Technology LAB., Sharif University of                      technology

2000 -to date               Research assistant, Thin Film Lab., University of Tehran

1) Fabrication of 0.1um physical gate length CMOS transistor with carbon nano_tube based        nano_lithography.

2) Study on Antimony, Aluminum and phosphorous Doping in low temperature.

3) Carbon nano_tube growth with PECVD system.

4) Studying the effect of electric field and UV illumination and external mechanical stress in crystallization of silicon in low temperature with assisted of Ni, Ge.

5) Design and fabrication of staggered and inverted staggered poly silicon TFT in low temperature.

6) Design and fabrication of vertical transistors.     

7) Work and repair of all of systems in thin film lab of University of Tehran and micro technology LAB of Sharif University.

8) Work on strain gauge, thermocouple, IR and MAP sensors.

9) Poly Silicon Thin film transistors fabrication assisted External Stress, UV Illumination, Hydrogenation, External Field at very low temperatures.

10) Carbon nano tube based Display Fabrication

11) Modeling of leakage current in VLSI circuits.

12) Study on fabrication of various photonic crystals (1-D, 2-D, 3-D)

13) Work in a research group in electronics, Rahmati research group in Tabriz, 1996 until 1999.

 

TEACHING

1998-2000       Teaching assistant, ECE Department, Sharif University Of  Technology

1) Electric Circuits 1, 2, for two consecutive terms.

2) Microprocessor LAB

 2003 to date      Lecturer Of Azad University ,Karaj 

1) Solid state electronic

2) Electronic measurement and instrumentation

3) Pulse & Switching Waveforms

 4) Electronics 

5) Electric Circuits 

 

Summary of some researches:

1)   Field Assisted Lateral Crystallization

- Reducing the process time and temperature by the assistance of an electric field.

- Top germanium layer acts as the seed of crystallization for the underlying silicon film.

- External electric field enhances the lateral growth.

- Unlike field aided metal induced lateral crystallization, where the growth starts from the negative electrode (cathode) and progresses towards the other side, the growth initiates from randomly distributed seeds and propagates in a circular fashion.

           

             2) Stress-Assisted Nickel-Induced Crystallization of Silicon on Glass

         External stress: compressive and tensile.

         Partial crystallization of amorphous silicon at temperatures less than 500oC.

         Nickel is used as the seed of crystallization.

         Deleterious effect of compressive stress (for 400 to 480oC).

         Tensile stress: enhancing growth from top to bottom.

                   

3) Metal-Free Hydrogenation Assisted Nano-Crystallization by RF PECVD

         Non-metal-induced crystallization of Si and Ge by means of successive hydrogenation /annealing treatments at UNAXIS™ PECVD apparatus.

         Temperatures: 150-200°C (Ge)/ 250-350°C (Si)

         Plasma power: 100-400W (0.08-0.32 W/cm2)

         Complete elimination of the deleterious effects of metal contamination.

         Sufficiently low crystallization temperature for growth on glass.

         Future applications to plastic substrates.

                                      

4) Silicon Crystallization Using UV Illumination

- External UV source is used for lowering the crystallization temperature of Silicon

 

5) Successfully Inverted Staggered TFT Fabrication

- Various poly silicon TFTs structures have been fabricated

 

6) PECVD growth of CNTs and Nano-Lithography

         Samples were grown by DC-PECVD on (100) Si.

         2 – 10 nm of Ni was used as a catalyst to convert C2H2 to C.

         T = 550 to 650˚C; P = 1 to 3 torr; Plasma current = 25 to 65 mA

 

 

         

7) 100nm Physical Gate Length CMOS Transistor Fabrication Using Carbon Nanotubes Based Nanolithography

         Source and drain definition, standard Lithography,

         Gate definition, nano-writing using nanotubes,

         Doping was done by deposition of thin heavily doped Sb/Ge layers,

         Excellent I-V characteristics are obtained, Best DIBL equal to 150mV/V, Drive Current equal to 312μA/μm and sub threshold slope equal to 200mV/decade.

         Threshold voltages of 0.05 and -0.05V are indication of small geometry device,

               - Fabrication Process

                                           

         

             

                - Transistor Electrical Characteristics

a) ID-VDS

 

 

b) Gate current shows no leakage current

  

c) ID-VGS: Sub threshold slope=200mV/decade  

 

 

 

d) ) ID-VGS at two drain source voltages, 1.1 V and 100mV . This figure illustrates DIBL parameter that is 150 mV/V

  

e) Gm that is dIDS/dVGS

 

f) Top and Cross of samples: SEM pictures

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 
 
 
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 
 

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